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2002 Microchip Technology Inc.
Preliminary
DS30485A-page 153
PIC18FXX39
16.4.8
I2C MASTER MODE START
CONDITION TIMING
To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended,
leaving the SDA line held low and the START condition
is complete.
16.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 16-19:
FIRST START BIT TIMING
Note:
If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I2C module is reset into its
IDLE state.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
SDA
SCL
S
TBRG
1st bit
2nd bit
TBRG
SDA = 1,
At completion of START bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit
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